This application claims the priority of Korean Patent Application No. 2003-16491, filed on Mar. 17, 2003, in the Korean Intellectual Property Office, the contents of which are incorporated herein in their entirety by reference.
1. Field of the Invention
The present invention relates to an apparatus which detects a frame synchronization signal in an optical disc system and a method of detecting the frame synchronization signal, and more particularly, to an apparatus and method for detecting a frame synchronization signal, capable of reducing errors in data demodulation in an optical disc system.
2. Description of the Related Art
Generally, a digital data signal reproduced from an optical disc has a frame structure divided by a frame synchronization signal and is subjected to EFM (Eight-to-Fourteen Modulation).
The EFM modulated digital data signal is input to the Digital Signal Processor (DSP) shown in FIG. 1 and is subjected to EFM modulation, error correction, error detection, descrambling, etc., by the DSP.
FIG. 1 is a block diagram of a general DSP. As shown in FIG. 1, the DSP 10 comprises an EFM demodulator 11, a Constant Linear Velocity (CLV) controller 14, an ECC unit 15, an interface 17, a descrambler 18, an EDC unit 19, and a transmitter 20.
The EFM demodulator 11 includes a frame synchronization signal detector 12 and a demodulator 13. The frame synchronization signal detector 12 detects a frame synchronization signal FRA_SYN from a digital data signal EFM input from an external source, and outputs the detected signal FRA_SYN to both the CLV controller 14 and the demodulator 13. The demodulator 13 aligns data in the frame of a received signal on the basis of the frame synchronization signal FRA_SYN.
The CLV controller 14 outputs a predetermined control signal CTL to a spindle motor driver (not shown) in response to the frame synchronization signal FRA_SYN. The spindle motor driver controls the rotation speed of a disc according to the control signal CTL.
Meanwhile, due to damage on the disk surface including scratches, finger-prints, black-dots, etc., a time interval can exist during which the frame synchronization signal FRA_SYN is not detected (that is, the frame synchronization signal FRA_SYN is deactivated at a logic 0). In the time interval during which the frame synchronization signal FRA_SYN is not detected, the CLV controller 14 determines that the rotational speed of the disc is slow, and outputs a predetermined control signal CTL for acceleration to the spindle motor driver. This can result in excessive increase of the rotational speed of the disc.
To solve this problem, a conventional method prevents the CLV controller 14 from being operated in error by inserting a predetermined frame synchronization signal during a predetermined time period in the time interval that the frame synchronization signal is not detected.
Referring to FIGS. 2 and 3, the configuration and operation of a frame synchronization signal detector according to a conventional technique will be described below.
FIG. 2 is a block diagram of a frame synchronization signal detector according to a conventional technique.
As shown in FIG. 2, the frame synchronization signal detector 30 comprises a synchronization signal detector 31, a window signal generator 32, a valid synchronization signal detector 33, an insertion synchronization signal generator 34, a frame synchronization signal output unit 35, and a counter 36.
The synchronization signal detector 31 detects and outputs a synchronization signal DET_SYN from a digital data signal EFM output from an RF amplifier (not shown). The window signal generator 32 enables a window signal WIND during a predetermined time period in response to a predetermined counting signal CNT. If the synchronization signal detector 31 outputs a synchronization signal DET_SYN in the time interval during which the window signal WIND is enabled, the valid synchronization signal detector 33 outputs the synchronization signal DET_SYN as a valid synchronization signal VAL_SYN, as shown in FIG. 3.
When the frame synchronization signal output unit 35 receives the valid synchronization signal VAL_SYN or an insertion synchronization signal INS_SYN, the frame synchronization signal output unit 35 outputs the received signal as a frame synchronization signal FRA_SYN.
The counter 36 is reset in response to the frame synchronization signal FRA_SYN, counts the rising edges or falling edges of a channel clock signal CH_CLK, and increases a count value. The counter 36 outputs the counting signal CNT when the count value reaches a predetermined value.
Whenever the frame synchronization signal FRA_SYN is detected (that is, the frame synchronization signal FRA_SYN is activated at a logic 1), the counter 36 is reset to have a count value of “zero” and restarts counting the rising edges or falling edges of the channel clock signal CH_CLK.
If the valid synchronization signal VAL_SYN is not detected during a predetermined time period, the insertion synchronization signal generator 34 generates a predetermined number of cycles of an insertion synchronization signal INS_SYN.
If the counting signal CNT is not received, the insertion synchronization signal generator 34 determines that the valid synchronization signal VAL_SYN is not detected. At this time, the counter 36 is not reset and continuously counts the rising edges or falling edges of the channel clock signal CH_CLK. As a result, the count value reaches the predetermined value.
When the count value reaches the predetermined value, the insertion synchronization signal generator 34 generates the insertion synchronization signal INS_SYN and resets the counter 36. The insertion synchronization signal generator 34 generates the insertion synchronization signal INS_SYN per a predetermined time interval.
If the insertion synchronization signal generator 34 outputs all the cycles of the insertion synchronization signal INS_SYN generated because the valid synchronization signal VAL_SYN was at a logic low, the window signal generator 32 enables the window signal WIND until a synchronization signal DET_SYN is detected. That is, the window signal generator 32 opens a window.
The operation of the conventional frame synchronization signal detector constructed above will be described with reference to FIG. 3. FIG. 3 is a timing diagram of main signals of the frame synchronization signal detector of FIG. 2.
In FIG. 3, “A” represents a waveform of the digital data signal EFM in a case where the disc surface is damaged, and “B” represents an excited interval.
As shown in FIG. 3, the synchronization signal DET_SYN is not detected during the “A” interval of the digital data signal EFM. The insertion synchronization signal generator 34 generates the predetermined number of cycles of the insertion synchronization signal INS_SYN during a predetermined time period, for example, in the interval denoted by “C” in FIG. 3. That is, instead of an actually detected synchronization signal DET_SYN, the frame synchronization signal detector 30 outputs the insertion synchronization signal INS_SYN as a frame synchronization signal. FRA_SYN during the “C” interval.
However, the frame synchronization signal detector 30 continuously outputs the insertion synchronization signal INS_SYN as the frame synchronization signal FRA_SYN until the window is open, although an actual valid synchronization signal DET_SYN is detected during in the “D” interval of FIG. 3. Also, the frame synchronization signal detector 30 does not output the actually detected valid synchronization signal DET_SYN as the frame synchronization signal FRA_SYN until the predetermined number of the cycles of the insertion synchronization signal INS_SYN is output during the “C” interval.
As a result, the demodulator 13 of FIG. 1 demodulates data based on the insertion synchronization signal INS_SYN, during the “D” interval. In this case, because the insertion synchronization signal. INS_SYN is not an actually detected value, the demodulator 13 cannot correctly demodulate data, which results in the generation of errors in data demodulation.